The sense amplifier array of the present invention detects and amplifies a bit line for loading data output from or externally from a cell array having at least two memory cells having a metal strapping region. A first bias potential for selectively supplying a constant voltage or a first voltage to the first and second bit line sense amplifiers according to an operating state, and the first bit line sensing amplifier according to an operating state. A second bias potentiometer selectively supplying a constant voltage or a second voltage to the first and second bit line sense amplifiers, and driven and controlled by a global restore control signal to drive the first and second bit line sense amplifiers, respectively. A pair of first drivers for generating a restore signal of a first voltage to drive the first bias potential, and the first and A pair of second drivers for driving the second bias potential by generating a sensing signal of a second voltage by driving control by a global sensing control signal for driving each of the two bit line sense amplifiers, and the bit line. And at least one bit line sense amplifier having equalization means for precharging to a voltage and equalizing the voltage supplied to the bit line.
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