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DESIGN METHOD OF LOW PASS IIR FILTER AND LOW PASS IIR FILTER

机译:低通IIR滤波器的设计方法

摘要

The present invention discloses a design method of a lowpass IIR filter and a lowpass IIR filter suitable for the same. The apparatus of the present invention includes a delayer 21 for receiving an input signal x (n) for a predetermined time delay, a shifter 22 for shifting the output of the delayer 21 by one bit to the MSB side, and a delayer 21. A delayer 23 for delaying the output of the predetermined time, a delayer 24 for receiving the output signal y (n) and a predetermined time delay, and a shifter for shifting the output of the delayer 24 to the MSB side by two bits ( 25, a delay 26 for delaying the output of the delayer 24 by a predetermined time, a subtractor 100 for subtracting the output of the shifter 25 from the output of the delayer 23, and a subtractor 100. A subtractor 200 for subtracting the output of the shifter 22 from the output of the adder, an adder 300 for adding the input signal x (n) and the output of the subtractor 200, and an output of the adder 300 and the coefficient c. A multiplier 350 for multiplying, a subtractor 400 for subtracting the output of the delayer 26 from the output of the delayer 24, a multiplier 450 for multiplying the output of the subtractor 400 and the coefficient 2t, multiplication The adder 500 adds the output of the machine 350 and the output of the multiplier 450, and the adder 600 adds the output of the adder 500 and the output of the delayer 26. here,; Is the critical frequency and Τ is the sampling time. Therefore, the present invention has the advantage that the size of the hardware is reduced due to the reduced number of multipliers.
机译:本发明公开了一种低通IIR滤波器的设计方法和适用于该低通IIR滤波器的低通IIR滤波器。本发明的设备包括:延迟器21,用于接收预定时间延迟的输入信号x(n);移位器22,用于将延迟器21的输出向MSB侧移位一位;以及延迟器21。用于延迟预定时间的输出的延迟器23,用于接收输出信号y(n)和预定时间延迟的延迟器24,以及用于将延迟器24的输出向MSB侧移位两位的移位器(25,延迟器26,用于将延迟器24的输出延迟预定时间;减法器100,用于从延迟器23的输出中减去移位器25的输出;减法器100。减法器200,用于将移位器的输出减去如图22所示,从加法器的输出,加法器300,用于将输入信号x(n)与减法器200的输出相加,以及加法器300和系数c的输出。乘法器350,用于相乘,减法器400用于从中减去延迟器26的输出。延迟器24的输出,用于将减法器400的输出和系数2t相乘的乘法器450,相乘。加法器500将机器350的输出与乘法器450的输出相加,并且加法器600将乘法器450的输出相加。这里,加法器500和延迟器26的输出。是临界频率,而Τ是采样时间。因此,本发明具有由于乘法器数量减少而减小硬件尺寸的优点。

著录项

  • 公开/公告号KR100195220B1

    专利类型

  • 公开/公告日1999-06-15

    原文格式PDF

  • 申请/专利权人 SAMSUNG ELECTRONICS CO LTD.;

    申请/专利号KR19960025217

  • 发明设计人 이제석;

    申请日1996-06-28

  • 分类号H03H17/00;

  • 国家 KR

  • 入库时间 2022-08-22 02:15:58

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