A process for the evaluation of test responses to be tested of digital circuits and circuit arrangement for carrying out the method

摘要

The method employs a logic circuit including a four-bit linear feedback shift register (R) with a feedback network (RN), a combinatorial logic element (LG), a buffer memory (ZS) and a comparator (V). The register has four D-type flip-flops (FF) in series. The comparator consists of four exclusive-OR gates (=1) with their outputs connected to an OR gate (-1). It delivers the result (TA) of comparison of the contents of the shift register and buffer memory when a binary 1 is supplied (AW) to its output AND gate (&).