The ramp generator has a digitally commanded oscillator (43) stabilised by a phase lock loop (400). A synthesised FM ramp (40) drives the digital phase comparator (41) of the phase lock loop. The synthesised FM digital ramp has a step response provided using a clock frequency (Fh) and an accumulator which provides staircase type steps with phase following a parabolic law set by the clock frequency. The digital comparator in the phase lock loop selects the strongest weighted bit for phase locking.
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