Cache performance improvement through the use of early select techniques and pipelining

摘要

A computer memory hierarchy comprises a level one (L1) cache with access/cycle time equal to or faster than a processor cycle time which can deliver at least a logical word or words needed by the processor on each cycle for an L1 HIT and an L2 cache including a directory and data array in which the L2 directory is accessed upon a MISS to the L1 cache. The L2 data array has a mapping from the L2 directory to the data array such that one block needs to be accessed from the data array, the L2 directory performing required address translation and, upon a HIT, starting access to the L2 array for a specific block required for reloading into the L1 cache, and upon a MISS, the L2 cache requesting a block reload from a next level of the hierarchy. The invention allows a DRAM L2 cache to be used in a computer memory hierarchy without compromising overall system performance. To achieve this, the total DRAM access is minimised as much as possible by use of early select techniques and pipelining. The larger DRAM capacity compared to a SRAM gives a substantially better HIT ratio which compensates for any small degradation due to access time.