Apparatus and method for addressing a cache memory in a computer system utilizing cache tag memory with integrated adder and pre-decode circuit

摘要

A tag memory circuit includes an address index input, an address offset input and an integrated adder and pre-decode circuit. The integrated adder and pre-decode circuit has a first addend input coupled to the address index input, a second addend input coupled to the address offset input, and a pre-decoded sum output. A final row decode and word line driver circuit is coupled to the pre-decoded sum output and generates a word line output which is coupled to the address inputs of a tag memory array. The data outputs of the tag memory array are coupled to a sense amplifier.