Sliced synchronous simulation engine for high speed simulation of integrated circuit behavior

摘要

A custom simulation engine is provided which operates upon a set of statically scheduled events. The simulation engine is automatically created from a functional description of the integrated circuit design. Each element of each partition within the functional description is analyzed and events related to the element are scheduled. The statically scheduled events are used to produce scheduled source code, which is then compiled to produce the simulation engine. VHDL or Verilog descriptions are similarly automatically created from the functional description. Subsequently, the VHDL or Verilog descriptions are synthesized into a netlist describing a final design of an integrated circuit. The entire process is automatic, and so the simulation engine and the netlist are functionally equivalent by construction. No simulation of the VHDL or Verilog descriptions is required as the present simulation engine correctly represents the design. Manual development of a custom simulation engine is eliminated. Additionally, the current simulation engine may enable software intended to be run upon the modeled integrated circuit to be executed prior to receiving hardware. Software and hardware may be concurrently designed and verified.