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Microprocessor system for handling multiple priority levels interrupt requests to processor and interrupt process identifiers
Microprocessor system for handling multiple priority levels interrupt requests to processor and interrupt process identifiers
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机译:微处理器系统,用于处理对处理器的多个优先级中断请求和中断进程标识符
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摘要
There is disclosed control circuitry for, and a method of controlling, multiple priority level interrupt request to a microprocessor in which output circuitry for outputting an interrupt identifier is operable only in response to an interrupt signal having a higher priority status than any currently executing interrupt process, and a microprocessor system and method of controlling a microprocessor system, incorporating such circuitry.
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