Microprocessor interrupt controller has means for processing interrupts such that requests of lower priority do not execute ahead of higher priority requests, provided they are still within their given latency time

摘要

Interrupt controller comprises parallel input (30) for receipt of a first interrupt request signal, means (31) for output of a second interrupt request signal as a reaction to the first interrupt request signal, state processing means (32) for determining interrupt priority, memory (37) for storing addresses of interrupt servicing programs whereby each servicing program handles an interrupt signal and means (36) for selection of an address based on the priority.