Defect insertion testability mode for IDDQ testing methods

摘要

A Defect Insertion Testability Mode for IDDQ Testing to detect defects in a semiconductor device and for accuracy correction during testing. In one embodiment of the present invention a screen condition and a known defect current are selected for the device under test (DUT). The DUT is screened without a known defect current being inserted and then is screened again with a known defect current inserted. The results of screening the DUT with and without the known defect current are then compared and the screen condition is adjusted based upon this comparison in order to increase the accuracy of the IDDQ test.