首页> 外国专利> Receiving a write request that allows less than one cache line of data to be written and issuing a subsequent write request that requires at least one cache line of data to be written

Receiving a write request that allows less than one cache line of data to be written and issuing a subsequent write request that requires at least one cache line of data to be written

机译:接收允许写入少于一个缓存数据行的写入请求,并发出一个后续写入请求,该请求要求至少写入一个缓存数据行

摘要

A computer system includes a memory device on the first data bus, a device that initiates on a second data bus a write transaction that can involve less than an entire cache line of data, and a bridge device that automatically converts the write transaction into one that requires an entire cache line of data and delivers the converted transaction to the first data bus.
机译:一种计算机系统,包括:第一数据总线上的存储设备;在第二数据总线上启动可能涉及少于整个数据高速缓存行的写事务的设备;以及自动将写事务转换为可写数据的桥设备需要整个数据缓存行,并将转换后的事务传递到第一条数据总线。

著录项

  • 公开/公告号US5903906A

    专利类型

  • 公开/公告日1999-05-11

    原文格式PDF

  • 申请/专利权人 COMPAQ COMPUTER CORPORATION;

    申请/专利号US19960659150

  • 发明设计人 CHRISTOPHER J. PETTEY;

    申请日1996-06-05

  • 分类号G06F13/14;

  • 国家 US

  • 入库时间 2022-08-22 02:08:11

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号