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Circuit for determining, in parallel, the terms of a remainder that results from dividing two binary polynomials
Circuit for determining, in parallel, the terms of a remainder that results from dividing two binary polynomials
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机译:并行确定由两个二进制多项式相除得到的余项的电路
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摘要
A circuit that determines the remainder of a modulo 2 polynomial division in just one clock cycle. Specifically, each term of the remainder is determined in parallel with each other term of the remainder. The circuit includes a network of XOR devices to determine H(X) =P(X) mod G(X), where P(X) is a first binary polynomial, of a form: a.sub. m X.sup.m +a.sub.m-1 X.sup.m-1 30 . . . +a.sub.0, where a={0,1} and X={0, 1}; G(X) is a second binary polynomial, of a form: a.sub.n X. sup.n +a. sub.n-1 X. sup.n-1 +. . . +a.sub.0, where a={0,1} and X={0,1}, and m n; and H(X) is a third binary polynomial, of a form: b.sub.p X. sup.p +b. sub.p-1 X. sup.p-1 + . . . +.sub.0. The configuration of the network of XOR devices is determined by reducing terms of the first binary polynomial to have only terms having less than the degree of the second binary polynomial. Then, for each term of the third binary polynomial (i. e., the remainder), it is determined which reduced terms of the first binary polynomial affect it. From this determination, the configuration of sub-networks of XOR devices is determined.
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机译:一种电路,可在一个时钟周期内确定模2多项式除法的余数。具体地说,余数的每一项与余数的每一项并行确定。该电路包括一个XOR器件网络,以确定H(X)= P(X)mod G(X),其中P(X)是形式为a的第一二进制多项式。 m X.m + a.m-1 X.m-1 30。 。 。 + a.sub.0,其中a = {0,1}和X = {0,1}; G(X)是第二个二进制多项式,形式为:a n X X sup n + a。 sub.n-1 X. sup.n-1 +。 。 。 + a.sub.0,其中a = {0,1}和X = {0,1},且m> n; H(X)是第三二进制多项式,其形式为:b p X sup p + b。 sub.p-1 X. sup.p-1 +。 。 。 + .sub.0。通过将第一二进制多项式的项减少为仅具有小于第二二进制多项式的度的项来确定XOR设备的网络的配置。然后,对于第三二进制多项式的每个项(即余数),确定第一二进制多项式的哪些简化项对其产生影响。根据该确定,确定XOR设备的子网的配置。
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