首页> 外国专利> Hierarchical routing method to be implemented in a layout system for a semiconductor integrated circuit and medium on which the hierarchical routing program is stored

Hierarchical routing method to be implemented in a layout system for a semiconductor integrated circuit and medium on which the hierarchical routing program is stored

机译:在用于半导体集成电路和介质的布局系统中实现的分层路由方法,在该半导体集成电路和介质上存储了分层路由程序

摘要

A hierarchical routing method is implemented in a layout system for a semiconductor integrated circuit which has a repetitive circuit portion. The hierarchical routing method lays out circuit elements for the repetitive circuit portion with the repetitive circuit portion structured hierarchically, expands the layout for the hierarchically- structured repetitive circuit portion in a separate independent database, extracts information of connections from the expanded layout for the repetitive circuit portion, and then carries out routing. Therefore, a semiconductor integrated circuit having a repetitive circuit portion can be designed in a short period of time while excellent properties are ensured for the semiconductor integrated circuit.
机译:在具有重复电路部分的半导体集成电路的布局系统中实现了分级布线方法。分层路由方法对具有重复结构的重复电路部分布置重复电路部分的电路元件,在单独的独立数据库中扩展分层结构的重复电路部分的布局,从重复电路的扩展布局中提取连接信息部分,然后执行路由。因此,可以在短时间内设计具有重复电路部分的半导体集成电路,同时确保该半导体集成电路的优异性能。

著录项

  • 公开/公告号US5905669A

    专利类型

  • 公开/公告日1999-05-18

    原文格式PDF

  • 申请/专利权人 FUJITSU LIMITED;

    申请/专利号US19970940005

  • 发明设计人 KEISUKE HORITA;

    申请日1997-09-29

  • 分类号G11C5/02;

  • 国家 US

  • 入库时间 2022-08-22 02:08:05

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