Performance analysis including half-path joining

摘要

Critical speed paths through a latch-based logic circuit must contain at least one latch-to-latch combinational delay which exceeds the nominal phase time of the circuit. To identify this set of paths through latch-to- latch delays greater than the nominal phase time of the circuit (i.e., through interesting tLLs), a half-path joining approach is employed. Backward half-paths from fixed timing points forward through the network defined by a latch abstraction of the circuit to an interesting tLL are multiplicatively joined with forward half-paths from the interesting tLL forward to other fixed timing points to form a set of fixed-point-to- fixed-point (F2F) paths through the interesting tLL. Timing analysis is performed on the set of F2F paths to identify those which represent critical speed paths through the circuit.