Algorithmic array mapping to decrease defect sensitivity of memory devices

摘要

A method and apparatus for addressing a memory device are described. A first logical address is translated into a first physical address to access a first storage location at a first row and a first column in an array of memory cells. A second logical address is translated into a second physical address to access a second storage location at a second row and a second column in the array of memory cells. The second row is separated from the first row by a row spacing factor. The second column is separated from the first column by a column spacing factor. The second level is separated from the first level by a level spacing factor. The row, column, and level spacing factors are chosen such that the first and second columns are physically distinct, the first and second rows are physically distinct, and the first and second storage locations do not share a same memory cell when the first and second logical addresses are sequential.