Method and system for conserving battery reserves in a navigation receiver by slowing and/or stopping the system clock during low demand

摘要

A battery-operated navigation satellite receiver with an antenna, a radio frequency stage, a down-converter, a digital signal processor and a microcomputer for demodulating L-band microwave carrier frequency spread spectrum transmissions from orbiting navigation satellites that each use their own unique pseudo-random number spreading code. The digital signal processor and a microcomputer each receive system clocks that can be varied in steps from full-speed down to any number of fractions including zero, or full stop. The system clocks to the digital signal processor and a microcomputer are lowered during periods of little or no acquisition or navigation activity. Scheduled updates, communication traffic, user activity, etc., are used to ramp the system clocks back up when the processing load demands it, e.g., when the tasks become CPU-bound at the current clock speed or when a particular task is predetermined to need the full processing speed capability of a particular navigation receiver. The slower system clocks have a direct correspondence with lowered power consumption demands by the digital signal processor and a microcomputer.