Using intelligent bus bridges with pico-code to service interrupts and improve interrupt response

摘要

A computer system having an improved method of handling interrupts associated with I/O operations to reduce interrupt latencies. The computer system includes one or more processing units, a memory device (e. g., RAM) connected to the processing unit via a system bus, and a plurality of I/O devices providing interrupt sources, connected to the processor via an I/O bus and a bus bridge. The bus bridge has incorporated therein or connected thereto means for intercepting interrupt requests transmitted to the processing unit and handling the interrupt requests without suspending the current process in the processing unit. In the preferred embodiment, the means for intercepting and handling the interrupts includes a storage device or array having pico-code instructions which are scheduled for execution in a sequencer by the interrupt control logic. If the pico-code sees an interrupt that it is not programmed to handle (such as an exception), it can pass that interrupt to the appropriate processing unit for handling. Additional bus bridges having pico-code instructions can be provided for multi-bus systems having additional interrupt sources connected via other busses.