USING INTELLIGENT BRIDGES WITH PICO-CODE TO IMPROVE INTERRUPT RESPONSE

摘要

The present invention is directed to a computer system with improved interrupt handling methods associated with I / O operations to reduce interrupt latency. The computer system provides one or more processing devices, a memory device (e.g., RAM) connected to the processing device by a system bus, interrupt sources and a plurality of I connected to the processor by an I / O bus and a bus bridge. / O devices are included. The bus bridge is integrated or connected to means for intercepting and processing interrupt requests sent to the processing device without disturbing the current process in the processing device. In a preferred embodiment, the means for intercepting and processing the interrupts comprises a storage device or array having pico code instructions scheduled by the interrupt control logic for execution in the sequencer. If an pico code sees an interrupt (such as an exception) that is not programmed to handle, the pico code can be handed over to the appropriate processing unit for that interrupt processing. An additional bus bridge with pico code instructions may be provided for a multibus system with additional interrupt sources connected by other buses.