Memory device including a column decoder for decoding five columns

摘要

A memory device including a plurality of memory cells, a plurality of bit lines, a plurality of bit line sense amplifiers, a plurality of column port gates, and a column decoder connected to a multiple of five column port gates. Each of the bit line sense amplifiers is connected to at least one of the bit lines and to at least one of the memory cells. Each of the column port gates is connected to at least one of the bit line sense amplifiers. The column decoder provides signals to the column port gates to which it is connected to select corresponding bit lines connected to the column port gates.