Logic circuit improvement manner and logic circuit improvement mode

摘要

PROBLEM TO BE SOLVED: To improve possibility of a semiconductor integrated circuit for fulfilling a constraint related with a delay time or wiring congestion. ;SOLUTION: Each kind of information necessary for logical design and layout design is inputted by an information inputting procedure 101. A design violation part is displayed by a design violation part display procedure 102. A partial circuit extraction area is set based on designation operated by a designer who refers to the display of the design violation part. Logic connection information in the partial circuit extraction area is extracted as a 'the logic connection information of a partial circuit' by a partial circuit extracting procedure 104. Logic optimization is operated in area priority/delay priority based on the logical connection information of the partial circuit by a partial circuit logic optimizing procedure 105. The logic-optimized partial circuit is substituted for the original partial circuit, and the re-layout of the partial circuit is operated, while an existing arrangement result is used, by a partial circuit re-layout procedure 106.;COPYRIGHT: (C)2000,JPO