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Inspection simplification design manner, bus error evasion design manner and integrated circuit

机译:检验简化设计方式,回避总线错误的设计方式及集成电路

摘要

PROBLEM TO BE SOLVED: To provide an inspection-facilitated designing method by which faults at the enable input of a tristate element provided for an integrated circuit can be inspected. ;SOLUTION: An observation circuit 10 composed of an exclusive OR (EXOR) tree 16 and a scan FF 17 dedicated to observation while having input terminals as many as the number of tristate elements 11 and 12 is arranged on the circuit of (a). The enable inputs of tristate elements 11 and 12 are connected to the input terminal of the EXOR tree 16, and the output terminal of the EXOR tree 16 is connected to the ordinary data input terminal of the scan FF 17 dedicated to observation. Further, the scan FF 17 dedicated to observation is inserted into an existent scan chain 18 composed of scan FF 18a and 18b [circuit (b)]. Thus, the presence/absence of any fault, which is conventionally hard to detect, at logic circuits 13 and 14 for controlling the enable inputs of restate elements 11 and 12 can be observed from an external, terminal through the scan chain 18.;COPYRIGHT: (C)1998,JPO
机译:要解决的问题:提供一种便于检查的设计方法,通过该方法可以检查为集成电路提供的三态元件的使能输入端的故障。解决方案:在(a)的电路上设置一个观察电路10,该观察电路10由异或(EXOR)树16和专用于观察的扫描FF 17组成,同时其输入端子的数量与三态元件11和12的数量相同。三态元件11和12的使能输入连接到EXOR树16的输入端子,EXOR树16的输出端子连接到专用于观察的扫描FF 17的普通数据输入端子。此外,将专用于观察的扫描FF 17插入由扫描FF 18a和18b [电路(b)]组成的现有扫描链18中。因此,可以通过扫描链18从外部端子观察在逻辑电路13和14处是否存在任何通常难以检测到的故障,该故障通常在逻辑电路13和14处用于控制重述元件11和12的使能输入。 :(C)1998,日本特许厅

著录项

  • 公开/公告号JP3003781B2

    专利类型

  • 公开/公告日2000-01-31

    原文格式PDF

  • 申请/专利权人 松下電器産業株式会社;

    申请/专利号JP19970214419

  • 发明设计人 細川 利典;

    申请日1997-08-08

  • 分类号G06F17/50;G01R31/28;

  • 国家 JP

  • 入库时间 2022-08-22 02:04:36

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