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Inspection simplification design manner, bus error evasion design manner and integrated circuit
Inspection simplification design manner, bus error evasion design manner and integrated circuit
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机译:检验简化设计方式,回避总线错误的设计方式及集成电路
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摘要
PROBLEM TO BE SOLVED: To provide an inspection-facilitated designing method by which faults at the enable input of a tristate element provided for an integrated circuit can be inspected. ;SOLUTION: An observation circuit 10 composed of an exclusive OR (EXOR) tree 16 and a scan FF 17 dedicated to observation while having input terminals as many as the number of tristate elements 11 and 12 is arranged on the circuit of (a). The enable inputs of tristate elements 11 and 12 are connected to the input terminal of the EXOR tree 16, and the output terminal of the EXOR tree 16 is connected to the ordinary data input terminal of the scan FF 17 dedicated to observation. Further, the scan FF 17 dedicated to observation is inserted into an existent scan chain 18 composed of scan FF 18a and 18b [circuit (b)]. Thus, the presence/absence of any fault, which is conventionally hard to detect, at logic circuits 13 and 14 for controlling the enable inputs of restate elements 11 and 12 can be observed from an external, terminal through the scan chain 18.;COPYRIGHT: (C)1998,JPO
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