TIMING SIMULATOR AND TIMING SIMULATION METHOD

摘要

PROBLEM TO BE SOLVED: To accurately and speedily specify delay data including the internal delay time of cells corresponding to the wiring form of cells by specifying the delay data including the internal delay time of cells from parameters including the number of branches and load capacity of wiring connected to the post step of cells.;SOLUTION: This timing simulator is composed of a display, keyboard, mouse and control part with a built-in hard disk storing the net list or formula of a semiconductor integrated circuit. Concerning such a timing simulator, the formula specifying the relation between the load capacity and internal delay time Td of cells 50 is prepared by the values of a number (n) of branches of wiring connected to the rear step of cells 50. Then, the number (n) of branches and load capacity of wiring connected to the post step of respective cells 50 are found from the net list of the semiconductor integrated circuit described at a gate level and according to the prepared formula, for each cell 50, the internal delay time Td is specified from the found number (n) of branches and load capacity of wiring.;COPYRIGHT: (C)2000,JPO