首页> 外国专利> LSI DESIGNING TECHNIQUE FOR PACKAGING INSPECTION

LSI DESIGNING TECHNIQUE FOR PACKAGING INSPECTION

机译:包装检查的LSI设计技术

摘要

PROBLEM TO BE SOLVED: To enable to detect at which terminal an anomaly has occurred by providing as inspecting circuit inside a LSI and detecting that the logical level of an unused input terminal becomes anomalous due to a mounting failure, etc. ;SOLUTION: The logical level of an output signal 'DCT' of a multiple-input NAND circuit 6 is observed. It is normal when the logical level is 'low', and an anomaly has occurred when it is 'high'. In the case that 'DCT' is 'high', only output signals 'DCT(2n-1)' (odd numbers) of an NAND circuit 5 are observed for specifying failure locations. In the case that only 'DCT3' is, for example, 'high' here, the location of 'NC-IN2' or 'NC-IN3' is suspected of developing a failure. 'DCT2' and 'DCT4' are further observed, and a failure has occurred in 'NC-IN2' in the case that 'DCT2' = 'high' and that 'DCT4' = 'low'. In the case that 'DCT4' = 'high' and that 'DCT2' ='low', a failure has occurred in 'NC-IN3'.;COPYRIGHT: (C)2000,JPO
机译:解决的问题:通过在LSI内部提供检查电路并检测由于安装故障等原因导致未使用的输入端子的逻辑电平变得异常,从而能够检测出哪个端子发生了异常;解决方案:逻辑观察到多输入与非电路6的输出信号“ DCT”的电平。当逻辑电平为“低”时,这是正常的;而当逻辑电平为“高”时,则发生了异常。在“ DCT”为“高”的情况下,仅观察到NAND电路5的输出信号“ DCT(2n-1)”(奇数)以指定故障位置。例如,在此处仅“ DCT3”为“高”的情况下,怀疑“ NC-IN2”或“ NC-IN3”的位置出现故障。进一步观察到“ DCT2”和“ DCT4”,并且在“ DCT2” =“高”且“ DCT4” =“低”的情况下,在“ NC-IN2”中发生了故障。在'DCT4'='高'和'DCT2'='低'的情况下,'NC-IN3'中发生了故障。;版权所有:(C)2000,JPO

著录项

  • 公开/公告号JP2000206199A

    专利类型

  • 公开/公告日2000-07-28

    原文格式PDF

  • 申请/专利权人 MATSUSHITA ELECTRIC IND CO LTD;

    申请/专利号JP19990010151

  • 发明设计人 MURAKAMI SHINICHI;

    申请日1999-01-19

  • 分类号G01R31/28;H01L21/82;H01L27/04;H01L21/822;

  • 国家 JP

  • 入库时间 2022-08-22 02:01:16

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号