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CMOS LOGIC CIRCUIT ELEMENT, SEMICONDUCTOR DEVICE AND ITS MANUFACTURE, AND METHOD FOR DESIGNING SEMICONDUCTOR CIRCUIT USED IN THE MANUFACTURE

机译:CMOS逻辑电路元件,半导体器件及其制造以及用于该制造中的半导体电路的设计方法

摘要

PROBLEM TO BE SOLVED: To provide a semiconductor device, which can be increased in operating speed and reduced in power consumption, even when the device is made finer and has a superior electrical characteristics, a method for manufacturing the device, and a method for designing a semiconductor circuit used in the method. ;SOLUTION: In a semiconductor device, a conductive region 3a is formed on the main surface of a semiconductor substrate 1. A first wiring layer 10a is electrically connected to the conductive region 3a, has a relatively short wiring length, and contains a material having a relatively high electrical resistance. A first insulator 11 is formed to surround the first wiring layer 10a and has a relatively low dielectric constant. A second wring layer 28a is formed on the main surface of the substrate 1, contains a material having an electrical resistance which is lower than that of the material contained in the first wiring layer 10a, and has a shorter wiring length than that of the layer 10a. Second insulators 24, 25, and 29 are formed so as to surround the second wiring layer 28a and have higher dielectric constants than that of the first insulator 11.;COPYRIGHT: (C)2000,JPO
机译:要解决的问题:提供一种半导体器件,其制造方法和设计方法,该半导体器件即使被制造得更细并且具有优异的电气特性,也可以提高操作速度并降低功耗。该方法中使用的半导体电路。 ;解决方案:在半导体器件中,在半导体衬底1的主表面上形成导电区域3a。第一布线层10a电连接到导电区域3a,具有相对短的布线长度,并且包含具有以下特征的材料:相对较高的电阻。第一绝缘体11形成为围绕第一布线层10a并且具有相对低的介电常数。在基板1的主面上形成有第二布线层28a,该第二布线层28a的电阻率比第一布线层10a所包含的材料的电阻低,并且布线长度比该层的布线长度短。 10a。第二绝缘体24、25和29被形成为包围第二布线层28a并且具有比第一绝缘体11更高的介电常数。;版权所有:(C)2000,JPO

著录项

  • 公开/公告号JP2000216264A

    专利类型

  • 公开/公告日2000-08-04

    原文格式PDF

  • 申请/专利权人 MITSUBISHI ELECTRIC CORP;

    申请/专利号JP19990014070

  • 发明设计人 AMISHIRO HIROYUKI;IGARASHI MOTOSHIGE;

    申请日1999-01-22

  • 分类号H01L21/8238;H01L27/092;H01L21/768;

  • 国家 JP

  • 入库时间 2022-08-22 01:59:11

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