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The reliable verification device and verification manner of the semiconductor integrated circuit and stores the verification program the storage

机译:半导体集成电路的可靠验证装置和验证方式及存储验证程序的存储器

摘要

A semiconductor integrated circuit reliability verification device for detecting any portion of design that may cause circuit malfunction due to the effects of switching noise, comprises a partial circuit network detecting part for detecting, based on a transistor-level net list for the circuit to be verified, information concerning partial circuit networks that form part of a circuit to be verified, a maximum resistance calculating part for calculating, based on the information concerning the partial circuit network, the maximum resistance that occurs while the channel connected component is operating, a gate capacitance calculating part for calculating, based on the information concerning the partial circuit network, the total gate capacitance for the portions but the inverter of a driven circuit, and an error judging part for calculating the value of evaluation function, based on the value of maximum resistance and the total gate capacitance, and judging whether or not the calculated value is in violation of the design criteria.
机译:一种用于检测可能由于开关噪声的影响而引起电路故障的设计的任何部分的半导体集成电路可靠性验证装置,包括用于根据要验证的电路的晶体管级网表进行检测的部分电路网络检测部分。 ,关于构成要验证的电路的一部分的部分电路网络的信息,最大电阻计算部分,用于基于关于部分电路网络的信息来计算在通道连接的组件工作时发生的最大电阻,栅极电容计算部分,用于基于与部分电路网络有关的信息,计算除驱动电路的逆变器之外的部分的总栅极电容;以及误差判断部分,用于基于最大电阻的值计算评估函数的值和总栅极电容,并判断是否计算d值违反设计标准。

著录项

  • 公开/公告号JP2996214B2

    专利类型

  • 公开/公告日1999-12-27

    原文格式PDF

  • 申请/专利权人 日本電気株式会社;

    申请/专利号JP19970236578

  • 发明设计人 村井 修三;

    申请日1997-08-18

  • 分类号G06F17/50;

  • 国家 JP

  • 入库时间 2022-08-22 01:57:35

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