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METHOD AND APPARATUS FOR REDUCED-COMPLEXITY VITERBI-TYPE SEQUENCE DETECTORS

机译:降低复杂度维特比型序列检测器的方法和装置

摘要

In a typical Viterbi demodulator implemented using the add, compare, select (ACS) method, each state in the expected sample sequence model is associated with a hardware module to perform the functions of adding new branch error metrics to path error metrics, comparing path error metrics, and selecting the path having the lowest path error metric. An ACS module may have two or more sequence-model states dynamically associated with it, such that at some times one sequence-model state is associated with it and at other times another sequence-model state is associated with it. This reduces the number of ACS modules required and also reduces the size/complexity of the demodulator's path memories which must store one path for each ACS module. Groups of sequence-model states may be chosen to share an ACS module without significant loss in performance as compared to the original, unreduced Viterbi demodulator.
机译:在使用添加,比较,选择(ACS)方法实现的典型Viterbi解调器中,预期样本序列模型中的每个状态都与硬件模块关联,以执行将新的分支错误度量添加到路径错误度量,比较路径错误的功能。指标,然后选择路径错误指标最低的路径。 ACS模块可能具有两个或多个与之动态关联的序列模型状态,这样,有时一个序列模型状态与它相关联,而在另一些时间,另一个序列模型状态与它相关联。这减少了所需的ACS模块的数量,还降低了解调器路径存储器的大小/复杂度,该路径存储器必须为每个ACS模块存储一条路径。与原始的未经简化的维特比解调器相比,可以选择一组序列模型状态来共享ACS模块,而不会在性能上造成重大损失。

著录项

  • 公开/公告号EP0663085B1

    专利类型

  • 公开/公告日2000-05-24

    原文格式PDF

  • 申请/专利权人 CIRRUS LOGIC INC;

    申请/专利号EP19930908314

  • 申请日1993-03-11

  • 分类号G06F11/10;H03M13/00;G11B20/18;G11B20/14;H04L25/49;H04L25/497;

  • 国家 EP

  • 入库时间 2022-08-22 01:49:05

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