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Digital signal processor architecture optimized for performing fast fourier transforms
Digital signal processor architecture optimized for performing fast fourier transforms
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机译:为执行快速傅立叶变换而优化的数字信号处理器架构
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摘要
A digital signal processor architecture particularly adapted for performing fast Fourier Transform algorithms efficiently. The architecture comprises dual, parallel multiply and accumulate units in which the output of the multiplier circuit portion of each MAC is cross-coupled to an input of the adder unit of the other MAC as well as to an input of the adder unit of the same MAC to which the multiplier belongs.
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