CIRCUIT FOR MEASURING ALLOWABLE ERROR AMOUNT OF CLOCK BIT RATE AND PREDICTING DECLINATION OF ALLOWABLE ERROR

摘要

Purpose a: circuit, its allowable error quantity for being used to measure a clock bit ratio and the previously positioned bias at one permissible range of prediction of an inclination for predicting an allowable error, an inclination of an allowable error quantity and one clock pulse frequency of hypothesis by measuring a clock being received. Construction a: circuit, its allowable error quantity for being used to measure a clock bit ratio simultaneously predicts that an inclination of an allowable error includes a phase comparator (100), its stage for comparing a reference clock (REF_CLK), the stage with a clock signal (RCV_CLK) externally applied. An output signal (S1) for one low-pass filter (110) receiving phase comparator (100), converted received signal (S1) enter a sine wave (S2). One differential part (120) receives sine wave (S2), and converted received signal (S2) enters a rectangular wave (S3). One pruning tool (130) receives the rectangular wave (S3) of differential part (120), the time judgement that event occurs. One timer section (140) receives an output signal (S4) of pruning tool (130), time output, and when a frequency plot of the clock signal of phase becomes equal. One inclination judging part (150) receives an output signal (S5) of timer section (140), judges whether that output signal (S5) is biased from an inclination adjusted of the frequency of an adjusting.