DSP HAVING ODD PARITY GENERATOR

摘要

PURPOSE: A DSP(digital signal processor) having an odd parity generator is provided to process data directly, used in a vector-matrix multiplication and then a modulo-2 calculation, in a hardware in order to reduce a segmentation and a reassembling step on the data, and also to reduce a calculation time by adopting an exclusive OR method in the vector-matrix multiplication. CONSTITUTION: A DSP with an odd parity generator comprises a program control unit(10), a data address arithmetic unit(20), an X-RAM(30), a Y-RAM(40), an X-address bus(XAB), and a Y-address bus(YAB). The program control unit(10) controls the DSPs. The data address arithmetic unit(20) determines the address for storing an X and Y data address and a result data according to the control of the program control unit(10). The X-RAM(30) and the Y-RAM(40) stores the X data and the Y data used in the arithmetic. The X-address bus(XAB) and the Y-address bus(YAB) is for transmitting the X data and the Y data.