X.25 NETWORK INTERFACING APPARATUS FOR X.25 PROTOCOL COMMUNICATION IN ELECTRONIC SWITCHING SYSTEM

摘要

PURPOSE: An X.25 network interfacing apparatus for an X.25 protocol communication in a full electronic switching system is provided to obtain an economical efficiency in a system construction by extending a port connected to a X.25 network according to a processing capacity of a microprocessor by mounting several X.25 link level controller chips each being operated as a master/slave and allowing a direct connection between the chips and the X.25 network. CONSTITUTION: A main microprocessor(2) reads a basic program and an application program stored in a system memory(10) and generates a general control signal. The system memory(10) stores the basic program and the application program, and also stores an IPC data in an HDLC format transmitted and received to and from a switching system and a data transmitted and received to and from an X.25 network. The first through the fourth X.25 network interface units(22,24,26,28) respectively mount an X.25 link level controller chip operated as a master and a slave so as to be connected to an external X.25 network and perform interfacing so that an interfacing circuit and the external X.25 network can communicate under the control of the microprocessor(2), a buffer controller or bus arbitration circuit unit(30). A switching system interfacing circuit unit(20) mounts a controller chip operated as a master and a slave therein to transmit and receive the IPC data in the HDLC format to and from the switching system, and interfaces to perform an IPC communication with the switching system under the control of the microprocessor(2), the buffer controller or bus arbitration circuit unit(30). A packet memory(14) stores the IPC data transmitted from the switching system and a packet data transmitted from the X.25 network, allows the packet data and the IPC data to be exchanged to each other by the microprocessor(2), the first through the fourth X.25 network interface units(20,22,24,26,28), and outputs the stored data to a corresponding unit under the control of the microprocessor(20). A packet data buffer(16) and a packet address buffer(18) control a data/address orientation by the second bus, and perform a function to accurately process while preventing a data/address collision between various devices. The buffer controller or bus arbitration circuit unit(30) controls internal buffers to control an input/output orientation of the data/address and arbitrates to prevent a collision of the data/address of the commonly used second bus.