Each run-length signal has a level of non-zero data value, and the first non-zero of the block of the predetermined number of run-length signals, in which a run of the number of zero-data connected to the non-zero data is disclosed. A zero-run develpping circuit for performing a zero-run develpping process to place a zero represented by a run between the data and the second zero-run data; A latch circuit for latching a predetermined number of non-zero data levels, a first write position generating circuit for generating a first latch position of the latch circuit, in which the first non-zero data is written in response to the first run length signal; And a second write position generating circuit for generating a second latch position of the latch circuit, in which the second non-zero data is written in correspondence with the first run length signal and the second run length signal.
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