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SEMICONDUCTOR DEVICE FOR SOI STRUCTURE HAVING LEAD CONDUCTOR SUITABLE FOR FINE PATTERNING

机译:SOI结构的半导体器件具有适用于精细图形化的铅导体

摘要

The present invention relates to a semiconductor device having a silicon on insulator (SOI) structure in which soft errors are less likely to occur. A semiconductor layer formed on an insulating substrate and having a major surface, the first layer having a plurality of semiconductor regions therein defined to be bonded to each other to form at least two homogeneous PN junctions, the junction being perpendicular to the insulating substrate; Extending in the direction and ending at the main surface of the semiconductor layer, the plurality of semiconductor regions constitute the main surface, each of the plurality of semiconductor regions having a width in a second direction parallel to the insulating substrate, and the first semiconductor region being the semiconductor layer. Has an extension region on the major surface of the first semiconductor region, the width of the major surface extension region of the first semiconductor region is larger than the width under the extension region of the first semiconductor region, and the second semiconductor region is bonded to the first semiconductor region and A semiconductor layer having an end surface constituting the end portion; A first lead conductor in contact with a first semiconductor region at a major surface of the semiconductor layer for electrical connection therebetween, comprising at least a first conductor layer and a second conductor layer, wherein the first conductor layer is formed of the first semiconductor region. Extends perpendicularly to the extension region while in physical and electrical contact with the extension region, the contact area between the first conductor layer and the extension region of the first semiconductor region is smaller than that of the major surface extension region of the semiconductor layer, and the second conductor A first lead conductor, wherein the layer extends over a portion of the semiconductor layer defining at least one of semiconductor regions other than the first semiconductor region; A second lead conductor in contact with the second semiconductor region at one end; The structure is provided on the second semiconductor region and has an end portion thereof that matches the end surface of the second semiconductor region, and includes an insulating film separating the first lead conductor and the second lead conductor.;As a result, the active region of the transistor can be miniaturized without being limited by the limitation of the pattern size of the electrode of the transistor, so that a transistor can be formed at high speed and hardly generate soft errors, and the pattern of the low concentration collector region can be greatly increased. By setting it, there exists an effect that a transistor with a high breakdown voltage can be comprised easily.
机译:本发明涉及一种具有绝缘体上硅(SOI)结构的半导体器件,其中,不太可能发生软错误。一种形成在绝缘衬底上并具有主表面的半导体层,第一层在其中具有被定义为彼此结合以形成至少两个均匀的PN结的多个半导体区域,该结垂直于绝缘衬底;多个半导体区域在该方向上延伸并终止于该半导体层的主表面,该多个半导体区域构成主表面,该多个半导体区域中的每个具有在第二方向上与绝缘基板平行的宽度,并且该第一半导体区域是半导体层。在第一半导体区域的主表面上具有延伸区域,第一半导体区域的主表面延伸区域的宽度大于第一半导体区域的延伸区域下方的宽度,并且第二半导体区域接合至第一半导体区域和具有端面构成端部的半导体层;在半导体层的主表面上与第一半导体区域接触以在其之间进行电连接的第一引线导体包括至少第一导体层和第二导体层,其中第一导体层由第一半导体区域形成。垂直于延伸区域延伸,同时与延伸区域进行物理和电接触,第一导体层与第一半导体区域的延伸区域之间的接触面积小于半导体层的主表面延伸区域的接触面积,并且第二导体是第一引线导体,其中该层在半导体层的一部分上延伸,该部分限定了除第一半导体区域以外的至少一个半导体区域。第二引线导体的一端与第二半导体区域接触。该结构设置在第二半导体区域上,并且其端部与第二半导体区域的端面匹配,并且包括将第一引线导体和第二引线导体分开的绝缘膜。可以不受晶体管电极图案尺寸的限制而使晶体管的尺寸最小化,从而可以高速形成晶体管并且几乎不产生软误差,并且低浓度集电极区域的图案可以是大大增加。通过设置,具有可以容易地构成击穿电压高的晶体管的效果。

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