Semiconducting memory element with address decoder has internal signal generator that activates internal main signal and trigger signal in response to activation of external main signal

摘要

The memory element has a memory cell field (37) with a number of memory cells, a signal generator arrangement for activating an internal main signal and a trigger signal, a pre-encoder (31) for pre-encoding a line address and outputting it and a main decoder (35) for decoding it and activating a word line trigger signal corresponds to a number of memory cells. The signal generator arrangement consists of an internal signal generator (33) that activates the internal main signal and the trigger signal in response to activation of the external main signal. The pre-encoder performs the line address pre-encoding and output during a deactivated state of the internal main signal. An Independent claim is also included for an address decoding method for a semiconducting memory element.