首页> 外国专利> Control circuit for data I/O buffer has control unit that controls I/O buffer so that data input buffer is deactivated in read mode and data output buffer is activated

Control circuit for data I/O buffer has control unit that controls I/O buffer so that data input buffer is deactivated in read mode and data output buffer is activated

机译:数据I / O缓冲器的控制电路具有控制I / O缓冲器的控制单元,以便在读取模式下禁用数据输入缓冲器,并激活数据输出缓冲器

摘要

The buffer has a data I/O contact point (21) for entering or outputting data, a data input buffer (22) for entering data received via the contact point into a SDRAM (25) on a control signal, a data output buffer (23) for outputting the data in the SDRAM via the I/O contact point and a control unit for (24) controlling the I/O buffer so that the data input buffer is deactivated in read mode and the data output buffer is activated.
机译:该缓冲器具有用于输入或输出数据的数据I / O接触点(21),用于将经由接触点接收的数据输入到控制信号上的SDRAM(25)中的数据输入缓冲器(22),数据输出缓冲器( 23)用于经由I / O接触点在SDRAM中输出数据,以及用于(24)控制I / O缓冲器的控制单元,使得在读取模式下数据输入缓冲器被停用并且数据输出缓冲器被激活。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号