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Control circuit for data I/O buffer has control unit that controls I/O buffer so that data input buffer is deactivated in read mode and data output buffer is activated
Control circuit for data I/O buffer has control unit that controls I/O buffer so that data input buffer is deactivated in read mode and data output buffer is activated
The buffer has a data I/O contact point (21) for entering or outputting data, a data input buffer (22) for entering data received via the contact point into a SDRAM (25) on a control signal, a data output buffer (23) for outputting the data in the SDRAM via the I/O contact point and a control unit for (24) controlling the I/O buffer so that the data input buffer is deactivated in read mode and the data output buffer is activated.
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