synchronous rückgekoppelte digitalschaltung with which have been minimized schaltverlustleistung

摘要

The novel synchronous feedback digital circuit has a minimized switching power loss. A data input receives an input data stream. A multiplicity of logic circuits and clocked registers are connected in a feedback loop between the data input and a data output. A clock generator generates an operating clock signal and a signal generating device generates phase-shifted clock signals for the clocked registers. The phase-shifted clock signals are phase shifted for the specific registers bywhere T is an operating clock period of the operating clock signal, N is a factor, i is a number of registers between the register clocked by the phase-shifted clock signal and the data input of the digital circuit.