DELAYED LOOP LOOPS AND METHODS WHICH EXCEED A DELAYED CLOCK SIGNAL BASED ON A REFERENCE PHASE VALUE

摘要

A controlled delay loop (20) which generates an advanced clock signal (ICLK2) synchronized with a reference clock signal (RCLK2) comprises an input buffer (21), a variable delay circuit (22), a delay compensation circuit (24), a phase shifter (23), a delay control device (25), a phase detection pump (26) and a phase reversal control device (27). The circuit (22) comprises a multiplicity of delay terminals, the number of validated delay terminals being controlled by a group of counting signals (QC). In the phase shifter (23), the phase of an output signal from the circuit (22) generates the signal (ICLK2) with a phase of the signal (RCLK2). When the compared phase difference is greater pi, the phase shifter 23 reverses a delayed clock signal (DCLK2) so as to generate the signal (ICLK2), and, when it is less than pi, the signal (DCLK2) n ' is not inverted, so as to be generated in the form of the signal (ICLK2).