Collection of output values of logic unit in electronic circuit, involves comprising using set of test cells of latch type connected to form shift register with displacement of values in two phases

摘要

The method involves using a set of latch type test cells which are connected to form a shift register, with displacement of values in two phases. The method of collection of logic values of outputs of a logic unit (10) with n inputs (E1,...,En) and p outputs (S1,...,Sp) contained in an electronic circuit (5) with p test cells (CT1,...,CTp) connected on one hand in parallel with respect to outputs of the logic unit so that the logic values are loaded to the test cells in normal mode, and on the other hand in series in a manner to constitute a shift register for the displacement of logic values to a collection node (TDO) in the test mode. In the first phase the logic values of one output of the logic unit by two are displaced in the shift register, and in the second phase the logic values of other outputs are displaced; the logic values of outputs of the logic unit are reloaded to the test cells between the first and second phases. Independent claims are included for a device for executing the method.