Dynamic logic memory addressing circuits, systems, and methods with reduced capacitively loaded predecoders

摘要

A memory configuration (10) for outputting information in response to an address (A0-A7), the configuration including an N wordline array of memory cells (12). The configuration further includes a plurality of predecoders (PD0, PD1, PD2), each operable to receive a corresponding portion of the address, and a plurality of decoder sets (DECODER SET 1- 8) having wordline enable outputs (WL.sub.0 -WL.sub.255). Each of the plurality of predecoders comprises a plurality of predecoder precharge nodes (e.g., PN.sub.0 -PN.sub.3), a plurality of predecoder conditional series discharge paths (e.g., TA5.sub.0, TA6.sub.01, and DT) and a plurality of predecoder inverters (e.g., INV.sub.0 -INV.sub.3). Each of the plurality of decoder sets comprises a plurality of decoder precharge nodes (e.g., PN.sub.0 -PN.sub.31), a plurality of decoder conditional series discharge paths (e.g., TPD2.sub.0/0, TPD1.sub.0/0-7, and TPD0.sub. 0/0-31), and a plurality of inverters (INV.sub.0 -INV.sub. 31). Each of the predecoder inverters has an inverter input and an inverter output, and comprises a p-channel transistor and an n-channel transistor. For one of the plurality of predecoders the output of each of its plurality of predecoder inverters is connected to provide a data signal to gates of an integer number D of n-channel transistors through a respective set of conductors each having a conductor capacitance C, wherein the integer number D of n-channel transistors are located in the plurality of decoder conditional series discharge paths and wherein each of the integer number D of n-channel transistors has a first load capacitance when the transistor is disabled and a second and greater load capacitance when the transistor is enabled. Lastly, the p-channel transistor in each of the predecoder inverters in each of the one of the plurality of predecoders is dimensioned to provide a drive capability of current to a load capacitance no greater than a value approximately equal to: ((1*the second load capacitance)+((D-1)*the first load capacitance)+ (D*C)).