Output data compression scheme for use in testing IC memories

摘要

A memory system operable in a normal mode of operation and a test mode of operation includes sensing circuitry which generates x number of data bits during a read cycle. A read path circuit, coupled to the sensing circuitry, transfers the x number of data bits generated by the sensing circuitry during a first read cycle in the normal mode of operation to x number of output nodes. A first detection circuit, coupled to the read path circuit, detects whether or not the x number of data bits generated by the sensing circuitry during a second read cycle in the test mode of operation are arranged in a pattern in which all bits are identical. A second detection circuit, coupled to the read path circuit, detects whether or not the x number of data bits generated by the sensing circuitry during the second read cycle in the test mode of operation are arranged in a pattern in which each two adjacent bits are different. An output circuit, coupled to the first and second detection circuits, generates y number of output data bits which are arranged in a pattern indicative of whether the x number of data bits generated by the sensing circuitry during the second read cycle in the test mode of operation are identical, are arranged in a pattern in which each two adjacent bits are different, or are arranged in another pattern, and wherein y is less than x. A method of testing an integrated circuit (IC) memory is also disclosed.