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Method for parallel-efficient configuring an FPGA for large FFTS and other vector rotation computations
Method for parallel-efficient configuring an FPGA for large FFTS and other vector rotation computations
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机译:用于大型FFTs和其他向量旋转计算的FPGA并行高效配置方法
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摘要
A method using replication of distributed arithmetic logic circuits and recursive interpolation of reduced angular increments of sine and cosine sum constants in logic look-up tables permits the computation of vector rotation and large FFTs in an efficient-parallel fashion within a unitary field programmable gate array chip, without off- chip memory for storing constants.
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