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Synchronous semiconductor device allowing reduction in chip area by sharing delay circuit
Synchronous semiconductor device allowing reduction in chip area by sharing delay circuit
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机译:共享延迟电路,可减少芯片面积的同步半导体装置
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摘要
A control signal generating circuit in a synchronous semiconductor memory device outputs timing signals for controlling activation of a word line and activation of sense amplifier, by delaying an external control signal by prescribed time periods. A bank control signal generating circuit provided for each bank holds activation of the timing signal from the control signal generating circuit, and outputs a signal for controlling timing of activation of the word line and timing of activation of the sense amplifier of the corresponding bank.
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