首页>
外国专利>
OTP (open trigger path) latchup scheme using buried-diode for sub- quarter micron transistors
OTP (open trigger path) latchup scheme using buried-diode for sub- quarter micron transistors
展开▼
机译:使用掩埋二极管的OTP(开放式触发路径)闩锁方案用于四分之一微米以下的晶体管
展开▼
页面导航
摘要
著录项
相似文献
摘要
Methods are described to prevent the inherent latchup problem of CMOS transistors in the sub-quarter micron range. Latchup is avoided by eliminating the low resistance between the V.sub.dd and V.sub.ss power rails caused by the latchup of parasitic and complementary bipolar transistor structures that are present in CMOS devices. These goals have been achieved without the use of guard rings by using p-region implants in the n-well to disconnect the pnp collector to npn base connection of two parasitic bipolar transistors. Further, the p-region implants are shorted to a reference voltage V.sub.ss via a p.sup.+ ground tab thus backbiasing the diode-like p-region implants. The proposed methods are compatible with CMOS processes.
展开▼