首页>
外国专利>
High speed register file organization for a pipelined computer architecture
High speed register file organization for a pipelined computer architecture
展开▼
机译:用于流水线计算机体系结构的高速寄存器文件组织
展开▼
页面导航
摘要
著录项
相似文献
摘要
A register file organization for a pipelined microprocessor is shown which includes a pipestage register interposed a global bit line and a register cell array of the register file in order to separate the delay associated with driving the global bit line, and devices attached to the global bit line, into a separate pipestage. Another register file organization is shown which includes a pipestage register that is interposed a register cell array and a decoder, which selects a register in the register cell array responsive to an instruction in an instruction register, to separate the decoder function and register cell array access times into different pipestages. The two approaches can be combined to separate the delay associated with the decoder, register cell array and global bit line into different pipestages in order to reduce the pipestage cycle time toward a fundamental minimum for pipelined computer architecture.
展开▼