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Integrated bus bridge and memory controller that enables data streaming to a shared memory of a computer system using snoop ahead transactions
Integrated bus bridge and memory controller that enables data streaming to a shared memory of a computer system using snoop ahead transactions
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机译:集成的总线桥接器和内存控制器,可使用监听活动将数据流式传输到计算机系统的共享内存
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摘要
A computer system having an integrated bus bridge and memory controller circuit and method for enabling access to a shared memory with high bandwidth data streaming are disclosed. The integrated bus bridge and memory controller circuit performs a series of snoop ahead transactions over a first bus during access transactions to the shared memory that originate over a second bus and thereby enables high bandwidth data streaming on the second bus. The integrated bus bridge and memory controller circuit includes a peripheral write buffer that buffers write data received over the second bus and that stores a snoop done flag for the write data that indicates whether a corresponding snoop ahead transaction for the write data is complete. The integrated bus bridge and memory controller circuit further includes a peripheral read prefetch buffer that prefetches read data during read transactions over the second bus only after a corresponding snoop ahead transaction for the read data is complete.
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