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Edge polysilicon buffer LOCOS isolation

机译:边缘多晶硅缓冲器LOCOS隔离

摘要

The present invention discloses an isolation method for fabricating isolation regions with less bird's peak sizes in semiconductor devices. A first pad oxide layer and a silicon nitride layer are first formed on a wafer substrate. After an undercut process is performed to the first pad oxide layer and forms a cave under the silicon nitride layer, a second pad oxide layer is formed over the wafer substrate. Next, a polysilicon layer is then deposited along the profile described above. Then, an anisotropic process is used to form sidewall spacers by etching the polysilicon layer. A recessed structure is then formed to the wafer substrate by a semi-isotropic process, and follows a thermal oxidation to fabricate isolation regions composed of silicon dioxide on the surface of the wafer substrate. The silicon nitride layer and the first pad oxide layer are then removed for continuing the active region processes.
机译:本发明公开了一种隔离方法,用于制造半导体器件中具有较小鸟峰尺寸的隔离区域。首先在晶片衬底上形成第一垫氧化物层和氮化硅层。在对第一垫氧化物层执行底切工艺并在氮化硅层下方形成空穴之后,在晶片衬底上方形成第二垫氧化物层。接下来,然后沿着上述轮廓沉积多晶硅层。然后,通过蚀刻多晶硅层,使用各向异性工艺来形成侧壁间隔物。然后通过半各向同性工艺在晶片基板上形成凹入结构,并进行热氧化以在晶片基板的表面上制造由二氧化硅组成的隔离区。然后去除氮化硅层和第一垫氧化物层以继续进行有源区工艺。

著录项

  • 公开/公告号US6133118A

    专利类型

  • 公开/公告日2000-10-17

    原文格式PDF

  • 申请/专利权人 ACER SEMICONDUCTOR MANUFACTURING INC.;

    申请/专利号US19980138298

  • 发明设计人 SHYE-LIN WU;

    申请日1998-08-21

  • 分类号H01L21/76;

  • 国家 US

  • 入库时间 2022-08-22 01:35:57

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