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Scalable architecture tester was adopted I-Cached SIMD technology
Scalable architecture tester was adopted I-Cached SIMD technology
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机译:可扩展架构测试仪被采用I-Cached SIMD技术
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摘要
A semiconductor tester high-speed system with Single Instruction-stream Multiple Data-stream (SIMD) organization, incorporating an event generator array, a plurality of pin channels for connecting to a device under test (DUT), a reconfigurable allocation switch for assignment of event generators to individual DUT pin channel connections, multi-clocking, and SIMD instruction cache. The result is a tester digital system exhibiting a maximum ratio of performance to hardware cost.
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