PROBLEM TO BE SOLVED: To accurately obtain the area of a minimum chip, by a method wherein data on an inner layout type of a chip is taken into consideration. ;SOLUTION: Data on a layout type are used as parameters, and an overall length L of wiring is calculated in a processor 9 through a calculation formula where L is a function represented by a gate use rate u and the number G of gates, wherein the total number GALL of gates of a target circuit obtained through a circuit data memory 6 is substituted for the number G. A total wiring track volume T is calculated through a calculation formula where T is a function represented by a gate use rate u and the number G of gates, wherein the total number GALL of gates is substituted for the number G of gates, and a gate use rate u which satisfies a formula, L=T, is obtained as a gate use rate limit uLIMiT, where L and T are obtained through the calculation formulas of the overall length L of wiring and the total wiring track volume T, and the total number GALL of gates is substituted for the number G of gates. A minimum chip are AMIN where a target circuit can be built in is obtained on the basis of the gate use rate limit uLIMiT.;COPYRIGHT: (C)1999,JPO
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机译:要解决的问题:为了通过一种考虑到芯片内部布局类型的数据的方法来精确地获得最小芯片的面积。 ;解决方案:将布局类型的数据用作参数,并在处理器9中通过计算公式计算出布线的总长度L,其中L是由栅极使用率u和栅极数量G表示的函数,其中通过电路数据存储器6获得的目标电路的门总数GALL替换为G。通过计算公式计算总布线轨迹量T,其中T是由门使用率u和G门数,其中门的总数GALL代替门数G,获得满足公式L = T的门使用率u作为门使用率限制uLIM i < / Sub> T,其中L和T是通过布线的总长度L和总布线迹线体积T的计算公式获得的,并且将栅极的总数GALL代入栅极的数量G。根据门限使用率限制uLIM i Sub> T获得可在其中内置目标电路的最小芯片AMIN。版权所有:(C)1999,JPO
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