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MULTI-PROCESSOR SYSTEM HAVING INDIVIDUAL AREA IN SHARED MEMORY

机译:在共享内存中具有单个区域的多处理器系统

摘要

PROBLEM TO BE SOLVED: To prevent the deterioration of processing capabilities, and to efficiently and economically structure a highly reliable and stable system in a multi- processor system in which the individual memory of each processor module is assigned as an individual area in a shared memory.;SOLUTION: This multi-processor system is provided with plural processor modules 10-0-10-n including at least one primary processor module 10-n and a shared memory 15 to be commonly used by each processor module. The shared memory 15 is provided with individual areas 17-0-17-n-1 assigned to each processor module, and a shared memory mapping table 16-1 and an address converting part 16-2 for converting memory access from each processor module into access to each individual area in the shared memory 15. Also, this multi- processor system is provided with a switching control part 18-1 for switching the assignment of the individual areas of the processor module in which any failure is generated and the primary processor module by monitoring each processor module.;COPYRIGHT: (C)2001,JPO
机译:要解决的问题:为防止处理能力下降,并在多处理器系统中高效经济地构建高度可靠和稳定的系统,在该系统中,每个处理器模块的单个内存被分配为共享内存中的单个区域解决方案:该多处理器系统具有多个处理器模块10-0-10-n,包括至少一个主处理器模块10-n和每个处理器模块共同使用的共享存储器15。共享存储器15设置有分配给每个处理器模块的各个区域17-0-17-n-1,以及共享存储器映射表16-1和地址转换部分16-2,用于将来自每个处理器模块的存储器访问转换为访问该共享存储器15中的每个单独区域。此外,该多处理器系统设置有切换控制部分18-1,该切换控制部分18-1用于切换产生任何故障的处理器模块和主处理器的单独区域的分配。通过监视每个处理器模块来访问该模块。版权所有:(C)2001,JPO

著录项

  • 公开/公告号JP2001166960A

    专利类型

  • 公开/公告日2001-06-22

    原文格式PDF

  • 申请/专利权人 FUJITSU LTD;

    申请/专利号JP19990351565

  • 发明设计人 IKEDA EIJI;KUMAGAI TOMONORI;

    申请日1999-12-10

  • 分类号G06F11/20;G06F15/177;

  • 国家 JP

  • 入库时间 2022-08-22 01:31:46

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