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CIRCUIT FOR OBTAINING ROOT OF QUADRATIC POLYNOMIAL ON FINITE BODY

机译:有限元上二次多项式求根的电路

摘要

PROBLEM TO BE SOLVED: To prevent a clock frequency of the total system including a circuit for obtaining roots of quadratic polynomial on finite body from being delayed corresponding to the operational delay of the circuit by shortening an apparent operational delay time. ;SOLUTION: This circuit on a finite body having a generation polynomial f=xn+xn-1+...+x+1 is constituted by arranging flip-flop circuits F1-F4 at every specific stages, for example every two stages of multistage gate circuits G1-G12. Consequently a delay time of the circuit becomes apparently a delay time between each flip-flop circuit and is shortened.;COPYRIGHT: (C)2000,JPO
机译:解决的问题:通过缩短视在操作延迟时间,防止包括用于获得有限主体上的二次多项式根的电路的整个系统的时钟频率对应于电路的操作延迟而延迟。 ;解决方案:该电路在具有生成多项式f = xn + xn-1 + ... + x + 1的有限物体上,是通过在每个特定阶段(例如,每2个阶段)布置触发器电路F1-F4来构成的多级门电路G1-G12。因此,电路的延迟时间显然变成了每个触发器电路之间的延迟时间,并且缩短了时间。;版权所有:(C)2000,JPO

著录项

  • 公开/公告号JP2000321978A

    专利类型

  • 公开/公告日2000-11-24

    原文格式PDF

  • 申请/专利权人 TOYO COMMUN EQUIP CO LTD;

    申请/专利号JP19990129729

  • 发明设计人 YANAGISAWA SHIGEKI;

    申请日1999-05-11

  • 分类号G09C1/00;G06F11/10;

  • 国家 JP

  • 入库时间 2022-08-22 01:28:34

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