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DATA PATH DESIGNING DEVICE AND LIBRARY THEREFOR

机译:数据路径设计设备及其图书馆

摘要

PROBLEM TO BE SOLVED: To improve the problem that the same logic has the same transistor constitution, is constituted of a library having the same transistor size ratio and it is difficult to automatically develop a data path having the minimum delay in a data path designing device using the self base library. ;SOLUTION: This device has a selector circuit assigning means 111 for virtually applying timing analysis to a net list prepared by a logic synthesizing means 121, analyzing a delay to the input on the control side of a selector circuit provided inside and a delay to the data input of the selector circuit and assigning the selector circuit of the light input load of a control signal when the delay to the control input side is greater or assigning the other selector circuit when the delay to the data input side is greater. Thus, the delay time from the control signal input can be improved and a further accelerated data path can be developed.;COPYRIGHT: (C)2001,JPO
机译:解决的问题:为了改善相同的逻辑具有相同的晶体管构成,由具有相同的晶体管尺寸比的库构成并且难以在数据路径设计装置中自动开发具有最小延迟的数据路径的问题。使用自助库。 ;解决方案:该设备具有选择器电路分配装置111,用于对由逻辑合成装置121准备的网表虚拟地进行时序分析,分析设置在内部的选择器电路的控制侧输入的延迟和对选择器电路的延迟。选择器电路的数据输入,当到控制输入侧的延迟较大时,为控制信号的轻输入负载分配选择器电路;或当到数据输入侧的延迟较大时,分配其他选择器电路。因此,可以改善来自控制信号输入的延迟时间,并可以开发出进一步的加速数据路径。;版权所有:(C)2001,JPO

著录项

  • 公开/公告号JP2001147949A

    专利类型

  • 公开/公告日2001-05-29

    原文格式PDF

  • 申请/专利权人 MATSUSHITA ELECTRIC IND CO LTD;

    申请/专利号JP19990329505

  • 发明设计人 MIYOSHI AKIRA;ARIGA YOSHITOSHI;

    申请日1999-11-19

  • 分类号G06F17/50;H01L21/82;

  • 国家 JP

  • 入库时间 2022-08-22 01:28:20

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